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CS5351 108 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture 24-Bit Conversion 108 dB Dynamic Range -98 dB THD+N System Sampling Rates up to 192 kHz Single-Ended Analog Inputs Less than 150 mW Power Consumption High Pass Filter or DC Offset Calibration Supports Logic Levels Between 5 and 1.8V Linear Phase Digital Anti-Alias Filtering Functionally Compatible with the CS5361
General Description
The CS5351 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24bit values for both left and right inputs in serial form at sample rates up to 192 kHz per channel. The CS5351 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The CS5351 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors. ORDERING INFORMATION CS5351-KS -10 to 70 C 24-pin SOIC CS5351-BS -40 to 85 C 24-pin SOIC CDB5351 Evaluation Board
VQ
REFGND
VL SCLK
LRCK SDOUT
MCLK
FILT+
Voltage Reference
Serial Audio Interface
RST LJ/I2S M/S HPF MDIV
AINL S/H
+ -
LP Filter
Digital Decimation Filter
High Pass Filter
DAC AINR S/H DAC + LP Filter Digital Decimation Filter High Pass Filter MODE0 MODE1
Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
(c)
APR `02 DS565PP1 1
CS5351
TABLE OF CONTENTS
1 PIN DESCRIPTIONS ................................................................................................................. 3 2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 4 3 APPLICATIONS ......................................................................................................................... 5 3.1 Operational Mode/Sample Rate Range Select .................................................................. 5 3.2 System Clocking ................................................................................................................ 5 3.2.1 Master Mode ......................................................................................................... 6 3.2.2 Slave Mode ........................................................................................................... 7 3.3 Power-up Sequence .......................................................................................................... 7 3.4 Analog Connections ........................................................................................................... 7 3.5 High Pass Filter and DC Offset Calibration ....................................................................... 8 3.6 Grounding and Power Supply Decoupling ......................................................................... 8 3.7 Synchronization of Multiple Devices .................................................................................. 8 4 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 9 ANALOG CHARACTERISTICS (CS5351-KS).......................................................................... 9 ANALOG CHARACTERISTICS (CS5351-BS)........................................................................ 10 DIGITAL DECIMATION FILTER CHARACTERISTICS .......................................................... 11 DC ELECTRICAL CHARACTERISTICS................................................................................. 14 DIGITAL CHARACTERISTICS ............................................................................................... 14 THERMAL CHARACTERISTICS............................................................................................ 14 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 15 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 16 5 PARAMETER DEFINITIONS ................................................................................................... 19 6 PACKAGE DIMENSIONS......................................................................................................... 20
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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1 PIN DESCRIPTIONS
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I2S/LJ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VQ3 AINR VQ2 VA GND VQ1 AINL TST M1 M0
Pin Name
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I2S/LJ M0 M1 TST AINR AINL VQ1 VQ2 VQ3 VA REFGND FILT+
# 1 2 3 4 5 6 8 9 10 11 12
Pin Description
Reset (Input) - The device enters system reset when enabled. Master / Slave Select (Input) - Selects operation as either clock master or slave. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power for the digital section.
7,18 Ground (Input) - Ground reference.
Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data (Output) - Output for two's complement serial audio data. Master Clock Divide (Input) - Enables a master clock divide by two function. High-Pass Filter Enable (Input) - Enables the Digital High-Pass Filter. Serial Audio Interface Format Select (Input) - Selects either the left-justified or I2S format for the SAI.
13, Mode Selection (Input) - Determines the operational mode of the device. 14 15
Test (Input) - Intended for testing only.
16, Analog Input (Input) - The full scale analog input level is specified in the Analog Characteristics specifi21 cation table. 17, Quiescent Voltage (Input/Output) - Filter connection for internal quiescent reference voltage. 20, 22 19 23 24
Analog Power (Input) - Positive power for the analog section. Reference Ground (Input) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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CS5351
2 TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V
+ 1 F
0.1 F
0.1 F
+
1 F
+5V to 1.8V
+5V
+
1 F
0.1 F
19 24
5.1
6
0.1 F
8
VA FILT+
VD
VL
47 F
+
0.1 F
23
REFGND RST
1 12 2 11 13 14 10
+
47 F
0.1 F
22 20
VQ3 VQ2 CS5351
LJ/I2S M/S HPF M0 M1 MDIV
Power Down and Mode Settings
17
VQ1
A/D CONVERTER
Left Analog Input
SDOUT
16
9
Audio Data Processor
30 2700 pF
AINL LRCK
3 4 5
*
SCLK MCLK
21
Right Analog Input
Timing Logic and Clock
30
2700 pF
AINR
*
GND T ST
15
GND
18
* Capacitors should be of the type COG or equivalent
7
Figure 1. Typical Connection Diagram
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3 APPLICATIONS 3.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2kHz to 192kHz. The CS5351 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 1.
Mode 1 0 0 1 1
Mode 0 0 1 0 1
MODE Single Speed Mode Double Speed Mode Quad Speed Mode Reserved
Output Sample Rate (Fs) 2kHz - 50kHz 50kHz - 100kHz 100kHz - 192kHz
Table 1. CS5351 Mode Control
3.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divide mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1.
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CS5351
3.2.1 Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 2. Refer to Table 2 for common master clock frequencies
/ 256 / 128 / 64 /1 MCLK /2 1 /4 MDIV /2 /1
Single Speed Double Speed Quad Speed Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
0 M1 M0
00 01 10
SCLK Output
Figure 2. CS5351 Master Mode Clocking
SAMPLE RATE (kHz) 32 44.1 48 64 88.2 96 176.4 192
DIV = 0 MCLK (MHz) 8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288
DIV = 1 MCLK (MHz) 16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576
Table 2. CS5351 Common Master Clock Frequencies
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3.2.2 Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3 for required clock ratios.
Mode 0 (SSM) MCLK/LRCK Ratio SCLK/LRCK Ratio 256x (512x)* 32x, 64x, 128x Mode 1 (DSM) 128x (256x)* 32x, 64x Mode 2 (QSM) 128x (256x)* 64x
*Available when MDIV = 1
Table 3. CS5351 Slave Mode Clock Ratios
3.3
Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance.
3.4
Analog Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to the Typical Connection Diagram which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. If active circuitry precedes the ADC, it is recommended that the above RC filter is placed between the active circuitry and the analog input pins. .
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CS5351
3.5 High Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5351 may generate a small DC offset into the A/D converter. The CS5351 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS5351 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5351.
3.6
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5351 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
3.7
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351's in the system. If only one master clock source is needed, one solution is to place one CS5351 in Master mode, and slave all of the other CS5351's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5351 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
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4 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (CS5351-KS) (TA = 25 C; Logic "0" = GND = 0 V; Logic "1" = VL = 5V; VA = 5V, VD = 3.3V, MCLK = 12.288 MHz, SCLK = 64 Fs, Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.)
Parameter Single Speed Mode Fs = 48kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Quad Speed Mode Fs = 192kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error Analog Input Characteristics Full-scale Input Voltage Input Impedance Note: 1. Referred to the typical full-scale input voltage HPF enabled HPF disabled Symbol Min 102 99 THD+N 102 99 THD+N 102 99 THD+N 0.95 18 -98 -85 -45 -95 95 0.0001 0.1 -92 dB dB dB dB dB Degree dB % ppm/C LSB LSB Vrms k -98 -85 -45 -95 108 105 102 -92 dB dB dB dB dB dB dB -98 -85 -45 108 105 102 -92 dB dB dB dB dB dB Typ 108 105 Max Unit dB dB
100
0 100 1.0 -
5
1.05 -
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CS5351
ANALOG CHARACTERISTICS (CS5351-BS) (TA = 25 C; Logic "0" = GND = 0 V; Logic "1" =
VL = 5V; VA = 5V, VD = 3.3V, MCLK = 12.288 MHz, SCLK = 64 Fs, Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.) Parameter Single Speed Mode Fs = 48kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Quad Speed Mode Fs = 192kHz Dynamic Range A-weighted unweighted 40kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 1) -1 dB -20 dB -60 dB 40kHz bandwidth -1dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage Input Impedance Symbol Min 101 98 THD+N 101 98 THD+N 101 98 THD+N 0.9 18 -98 -85 -45 -95 95 0.0001 0.1 -91 dB dB dB dB dB Degree dB % ppm/C LSB LSB Vrms k -98 -85 -45 -95 108 105 102 -91 dB dB dB dB dB dB dB -98 -85 -45 108 105 102 -91 dB dB dB dB dB dB Typ 108 105 Max Unit dB dB
100
0 100 1.0 -
5
1.1 -
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DS565PP1
CS5351
DIGITAL DECIMATION FILTER CHARACTERISTICS
Parameter Single Speed Mode (2kHz to 50kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Double Speed Mode (50kHz to 100kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency Quad Speed Mode (100kHz to 192kHz sample rates) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 2. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. 3. The filter frequency response scales precisely with Fs. -3.0 dB -0.13 dB @ 20Hz (Note 2) (Note 2) 1 20 10 10 /Fs
4
Symbol (Note 3) (Note 3) tgd tgd (Note 3) (Note 3) tgd tgd (Note 3) (Note 3) tgd tgd
Min 0 0.579 -95 0 0.670 -92 0 0.775 -97 -
Typ 12/Fs 9/Fs 5/Fs -
Max 0.469 0.035 0.0 0.45 0.035 0.0 0.245 0.035 0.0 0
Unit Fs dB Fs dB s s Fs dB Fs dB s s Fs dB Fs dB s s Hz Hz Deg dB s
(-0.1 dB)
(-0.1 dB)
(-0.1 dB)
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CS5351
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 3. Single Speed Mode Stopband Rejection
0
Figure 4. Single Speed Mode Transition Band
0.10
-1
0.08
-2
0.05
-3
Amplitude (dB)
-5
Amplitude (dB)
0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
-4
0.03
0.00
-6
-0.03
-7
-0.05
-8
-9
-0.08
-10 0.45
Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 5. Single Speed Mode Transition Band (Detail)
0 -10 -20 -30 -40 -50 Amplitude (dB)
Figure 6. Single Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
-60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 7. Double Speed Mode Stopband Rejection
Figure 8. Double Speed Mode Transition Band
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0
0.10
-1
0.08
-2
0.05
-3
Amplitude (dB)
-5
Amplitude (dB)
0.43 0.45 0.48 Frequency (normalized to Fs) 0.50 0.53 0.55
-4
0.03
0.00
-6
-0.03
-7
-8
-0.05
-9
-0.08
-10 0.40
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 9. Double Speed Mode Transition Band (Detail)
Figure 10. Double Speed Mode Passband Ripple
0 -10 -20 -30 -40 Amplitude (dB) -50 -60 -70 -80
Amplitude (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
-90 -100 -110 -120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
-100 -110 -120 -130 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Frequency (normalized to Fs)
Figure 11. Quad Speed Mode Stopband Rejection
0
Figure 12. Quad Speed Mode Transition Band
0.10
-1
0.08
-2
0.06
-3
0.04
Amplitude (dB)
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
Amplitude (dB)
-4
0.02
-5
0.00
-6
-0.02
-7
-0.04
-8
-0.06
-9
-0.08
-10 Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 13. Quad Speed Mode Transition Band (Detail)
Figure 14. Quad Speed Mode Passband Ripple
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CS5351
DC ELECTRICAL CHARACTERISTICS (GND = 0V, all voltages with respect to ground.
TA = 25 C; MCLK=12.288 MHz; Master Mode)
Parameter DC Power Supplies: Positive Analog Positive Digital Positive Logic VA VL,VD = 5 V VL,VD = 3.3V VA VL,VD=5V VL, VD=5V VL, VD = 3.3V (Power-Down Mode) (1 kHz) (Note 5) Symbol VA VD VL IA ID ID IA ID PSRR Min 4.75 3.1 1.7 Typ 5.0 17.5 22 14.5 2 2 198 135 20 65 2.5 50 0.01 5 35 0.01 Max 5.25 5.25 5.25 21 26 17 235 161 Unit V V V mA mA mA mA mA mW mW mW dB V
Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode)(Note 4) Power Consumption (Normal Operation)
Power Supply Rejection Ratio
VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
k
mA V
k
mA
Notes: 4. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 2 mA Low-Level Output Voltage at Io = 2 mA Input Leakage Current
(TA = 25 C) Symbol (% of VL) (% of VL) VIH VIL VOH VOL Iin Min 70% VL - 1.0 Typ Max 30% 0.4 10 Units V V V V A
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance Ambient Operating Temperature (Power Applied) -KS -BS Symbol Min -10 -40 Typ 70 Max 135 +70 +85 Unit C C/W C C
JA
TA TA
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ABSOLUTE MAXIMUM RATINGS
Parameter DC Power Supplies: Analog Logic Digital (Note 6) (Note 7) (Note 7) -KS -BS (GND = 0V, All voltages with respect to ground.) Symbol VA VL VD Iin VIN VIND TA TA Tstg Min -0.3 -0.3 -0.3 GND-0.7 -0.7 -20 -50 -65 Typ Max +6.0 +6.0 +6.0 10 VA+0.7 VL+0.7 +85 +95 +150 Units V V V mA V V C C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 6. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 7. The maximum over/under voltage is limited by the input current. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS5351
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (TA = 25 C; Logic "0" =
GND = 0 V; Logic "1" = VL = VA = 5 V, VD = 3.3V, CL = 20 pF) Parameter MCLK Period MCLK Pulse Width High MCLK Pulse Width Low Master Mode SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle LRCK Duty Cycle Slave Mode Single Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge Double Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge Quad Speed Output Sample Rate LRCK Duty Cycle SCLK Period SCLK High/Low SCLK falling to SDOUT valid SCLK falling to LRCK edge tsclkw tsclkhl tdss tslrd Fs 100 40 81 20 -10 50 192 60 20 10 kHz % ns ns ns ns tsclkw tsclkhl tdss tslrd Fs 50 40 163 20 -20 50 100 60 40 20 kHz % ns ns ns ns tsclkw tsclkhl tdss tslrd Fs 2 40 163 20 -20 50 50 60 40 20 kHz % ns ns ns ns tmslr tsdo -20 0 50 50 20 40 ns ns % % Symbol tclkw tclkh tclkl Min 40 15 15 Typ Max 1953 Unit ns ns ns
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t sclkh t sclkl
SCLK output t mslr LRCK output t sdo SDOUT MSB MSB-1
SCLK input t sl rd LRCK input t lrdss S DOUT MSB MSB-1 t dss MSB-2 t sclkw
Figure 15. Master Mode, Left Justified Serial Audio Interface
Figure 16. Slave Mode, Left Justified Serial Audio Interface
t sclkh t sclkl
SCLK output t mslr LRCK output t sdo SDOUT MSB
SDOUT
LRCK input t dss MSB MSB-1 SCLK input t sclkw
Figure 17. Master Mode, I2S Serial Audio Interface
Figure 18. Slave Mode, I2S Serial Audio Interface
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CS5351
LRC K
L e ft C h a n n e l
R ig h t C h a n n e l
SC L K
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. Left-Justified Serial Audio Interface
LR CK L e ft C h a n n e l R ig h t C h a n n e l
SCLK
SD A TA
2 3 22
9
8
7
6
5
4
3
2
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Figure 20. I2S Serial Audio Interface
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DS565PP1
CS5351
5 PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
DS565PP1
19
CS5351
6 PACKAGE DIMENSIONS
24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0 8
20
DS565PP1
* Notes *

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